Design & Reuse
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1020 IP
1001
0.0
PSRAM/SD3.0/EMMC5.1 IO in SMIC 28HKD 0.9/2.5V, upto 600Mbps
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1002
0.0
SSTL_15_18 IO Pad Set
The SSTL_15/18 pad set is a full complement of I/O, calibration, power, and spacer cells that are necessary to assemble a padring by abutment. Since t...
1003
0.0
Standard Cell Libraries, GF 55nm
Silvaco’s Standard Cell libraries deliver thousands of highly optimized cells with each one being optimized for power, area, speed, routing, and yield...
1004
0.0
SUB-LVDS TX PHY
The InPsytech Low-Voltage Differential Signaling (LVDS) is a well-established high-speed interface known for its excellent combination of fast data ra...
1005
0.0
subLVDS IO Pad Set
The LVDS I/O is a three-module design (input, output and reference block). The LDP_OU_450_18V_T is a 1400MBit/s LVDS Driver, LDP_IN_450_18V_DN is a 14...
1006
0.0
LVDS I/O Buffer 40/28/22/16/7nm
The LVDS I/O has driver and receiver of TSMC 7, 16, 22, 28, 40nm and Samsung 14nm process. ● Support LVDS specification is TIA/EIA-644-A. ● LVDS dri...
1007
0.0
LVDS IO in SMIC 28HKC+, upto 1.6Gbps
LVDS IO can be applied for various die-to-die interface communication. Brite LVDS IO libraries can support data rate up to 2000Mbps with 2.5V and 1.8V...
1008
0.0
LVDS IO in SMIC 40NLL, upto 800Mbps
LVDS IO can be applied for various die-to-die interface communication. Brite LVDS IO libraries can support data rate up to 2000Mbps with 2.5V and 1.8V...
1009
0.0
LVDS IO Pad Set
The LVDS I/O is a three-module design (input, output and reference block). The LDP_OU_675_25V_T is a 2GBit/s LVDS Driver, LDP_IN_675_25V_DN is a 2GBit...
1010
0.0
LVDS Rx IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS Receiver. This IP consists of 20-lane (4 x 4D1C) LVDS receivers and supports up to 1.5Gbps data rate. The input clock is ...
1011
0.0
LVDS RX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
1012
0.0
LVDS Tx and OpenLDI Tx (Automotive IP)
InPsytech Inc., an Automotive interface IP solution provider, introduces its latest Automotive High-Speed Interface IP Series, designed to meet the ri...
1013
0.0
LVDS TX Combo TTL PHY
Innosilicon LVDS implements LVDS TIA/EIA protocol. Normally, Innosilicon LVDS contains four 7-bit parallel-load serial-out shift registers, a 7X clock...
1014
0.0
LVDS TX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
1015
0.0
LVDS TX+ (Transmitter) in UMC 40LP
The MXL-LVDS-SR-TX+ is a high performance 4-channel LVDS transmitter implemented using digital CMOS technology. With a maximum transmit clock frequenc...
1016
0.0
LVDS/ MIPI Combo PHY IP, Silicon Proven in SMIC 40LL
The MIPI-LVDS Combo Tx IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can be eas...
1017
0.0
LVDS/FPD Link IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS transmitter. This IP consists of 20-lane (4 x 4D1C) LVDS drivers and supports up to 1.5Gbps data rate. In LVDS mode, both...
1018
0.0
LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe
A transmitter for LVDS with a physical layer IP. This IP has 20 lanes (4 x 4D1C) of LVDS drivers and can handle 1.5Gbps of data rate. Both serial and ...
1019
0.0
LVDS/TTL PHY & Controller
INNOSILICON™ LVDS/TTL IP implements the LVDS TIA/EIA protocol, providing a low-voltage, high-speed point-to-point signal interface. It supports either...
1020
0.0
Synopsys High-Speed Test IO in TSMC N3P
AI and HPC are transitioning to chiplet-based designs to overcome scaling limits of monolithic SoCs and achieve superior performance. While heterogene...